This application claims priority under 35 USC §119 to Korean Patent Application No. 2006-115386 filed on Nov. 21, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to switched capacitor circuits, and more particularly, to a switched capacitor circuit implemented with a single ended inverter and an offset unit for rendering a node as virtual ground.
2. Background of the Invention
A switched capacitor circuit is generally a type of filter that is comprised of capacitors and switches without any inductor or resistor. A switched capacitor circuit is amenable to be fabricated with the complementary metal-oxide-semiconductor (CMOS) process. A switched capacitor circuit is easily integrated with the CMOS process in a single chip without resistors and is amenable for decreased power consumption.
In addition, a switched capacitor circuit uses a capacitor instead of a resistor that may result in higher error, for improving accuracy when a single integrated circuit chip is fabricated during a CMOS process. Switched capacitor circuits are developing along with CMOS analog circuit technology, and are widely employed for processing analog signals such as for communication-specific LSI for example.
FIG. 1 shows a general switched capacitor circuit 10 according to the prior art. Referring to FIG. 1, the switched capacitor circuit 10 includes an operational-transconductance amplifier (OTA), a plurality of switches S1, S2, S3, S4, and S5, and a plurality of capacitors C1 and C2.
The switched capacitor circuit 10 operates with a first set of switches S1, S3, and S5 being closed when a first switch control signal (D1 is activated to the logic high state (and being open otherwise). A second set of switches S2 and S4 are closed when a second switch control signal φ2 is activated to the logic high state (and are open otherwise).
When the first set of switches S1, S3, and S5 are closed with the second set of switches S2 and S4 being open, the capacitor C1 accumulates charge corresponding to an input signal Vi while the capacitor C2 is reset. Subsequently when the second set of switches S2 and S4 are closed with the first set of switches S1, S3, and S5 being open, charge is transferred to the capacitor C2 from the capacitor C1 for satisfying the following equation:
            V      o              V      i        =            C      1              C      2      Vo is an output signal generated at an output node of the OTA. C1 is the capacitance of the capacitor C1, and C2 is the capacitance of the capacitor C2.
The switched capacitor circuit 10 is widely used in analog circuits such as an integrator, an adder, or an amplifier for example with relatively small errors. The switched capacitor circuit 10 is also used in a discrete-time analog filter, an analog-to-digital converter, and a digital-to-analog converter.
The switched capacitor circuit 10 uses the OTA in a feedback loop. However, the OTA consumes much power and occupies a large circuit area in the switched capacitor circuit 10.